module div(clk, rstn, clkout);
input clk; //系统时钟
input rstn; //收入复位信号
output clkout; //采样时钟输出
reg clkout;
reg [15:0] cnt;
/////分频进程, 50Mhz 的时钟 326 分频/////////
always @(posedge clk or negedge rstn) 
begin
 if (!rstn) begin
 clkout <=1'b0;
  cnt<=0;
 end 
 else if(cnt == 16'd162) begin
 clkout <= 1'b1;
 cnt <= cnt + 16'd1;
 end
 else if(cnt == 16'd325) begin
 clkout <= 1'b0;
 cnt <= 16'd0;
 end
 else begin
 cnt <= cnt + 16'd1;
 end
end
endmodule 